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HCPL-7601/7611
CMOS/TTL Compatible, Low Input Current, High Speed, High CMR Optocoupler
Data Sheet
Description The HCPL-7601/11 is a low input current version of the HCPL-2601/11 and 6N137 (without enable). The optically coupled gates combine an AlGaAs highefficiency light emitting diode and an integrated high gain photon detector to create a low input current device for low power applications. The output of the detector IC is an open collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 10,000 V/s (HCPL-7611). This unique design provides maximum ac and dc circuit isolation while achieving CMOS and TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40C to 85C with no derating required allowing trouble free system performance. This product is suitable for high speed logic interfacing, input/output buffering, and applications that require low input-current switching levels. Schematic
IF 2+ IO 6 ICC 8 VCC VO
Features * Low input current version of HCPL-2601/11 and 6N137 * Wide input current range: IF = 2 mA to 10 mA * CMOS/TTL compatible * Guaranteed switching threshold: IF = 2 mA (max.) * Internal shield for high Common Mode Rejection (CMR) HCPL-7601: 5,000 V/s (typical) at VCM = 50 V, IF = 4 mA HCPL-7611: 15,000 V/s (typical) at VCM = 1000 V, IF = 4 mA * High speed: 10 Mbd typical * Guaranteed ac and dc performance over temperature: -40C to 85C * IEC/EN/DIN EN 60747-5-2 approval: VIORM = 600 VRMS * UL recognized: 3750 VRMS, 1 minute * CSA accepted * Low supply current requirement * Low TPSK: 40 ns guaranteed * Lead-free option "-000E" Applications * Isolated line receiver * Simplex/multiplex data transmission * Programmable logic controllers * Computer-peripheral interface * Microprocessor system interface * Digital isolation for A/D, D/A conversion * Switching power supply * Instrument input/output isolation * Ground loop elimination * Pulse transformer replacement
VF 3HCPL-7601/11 SHIELD USE OF A 0.1 F BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1). TRUTH TABLE (POSITIVE LOGIC) OUTPUT LED L ON H OFF 5 GND
CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
The HCPL-7601/11 family offers many features that are especially beneficial to system designers. The low input current requirements and guaranteed switching threshold (2 mA max.) allows the LED to be driven directly by any standard high-speed CMOS gate (e.g. 74HC/HCT). This will simplify designs by eliminating the need for special driver circuits and result in lower part counts and greater system reliability while freeing up valuable printed circuit board space. The wide current input range of 2 mA to 10 mA and guaranteed ac and dc performance over a wide temperature range will also simplify designs. Low supply current requirements mean lower power dissipation allowing for the use of a smaller, less expensive power supply. The high speed (10 Mbd typ.) and low propagation delay skew (Tpsk 40 ns guaranteed) allow for easier design of high speed parallel applications. The world-wide regulatory approval (UL/CSA/IEC/ EN/DIN EN 60747-5-2) will facilitate the acceptance of the end product in international markets.
Regulatory Information The HCPL-7601 and HCPL-7611 have been approved by the following organizations: UL Approved under UL 1577, component recognition FILE E55361). IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 This optocoupler is suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Can be used for safe electrical separation between ac mains and SELV (safety extra-low voltage) in equipment according to the following specifications: DIN VDE 0804/05.89 DIN VDE 0160/05.88 Reference voltage (VDE 011b Tab 4): 630 Vac. CSA Approved under CSA22.2 No. 0 General Requirements, Canadian Electrical Code, Part II; and CSA Component Acceptance Notice #5, File CA 88324.
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Ordering Information HCPL-7xxx is UL Recognized with 3750 Vrms for 1 minute per UL1577 and is approved under CSA Component Acceptance Notice #5, File CA 88324. Option Part RoHS non RoHS Number Compliant Compliant Package HCPL-7601 -000E no option 300 mil DIP-8 HCPL-7611 -300E #300 -500E #500
Surface Mount X X
Gull Wing X X
Tape & Reel
UL 5000 Vrms/ 1 Minute rating
X
IEC/EN/DIN EN 60747-5-2 Quantity 50 per tube 50 per tube 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-7611-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant. Example 2: HCPL-7601 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use `-XXXE.'
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Absolute Maximum Ratings (No Derating Required up to 85 C) Storage Temperature ....................................................... -55 C to +125 C Operating Temperature ..................................................... -40 C to +85 C Lead Solder Temperature ................................................... 260 C for 10 s (1.6 mm below seating plane) Average Input Current - IF (See Note 2.) ........................................ 20 mA Reverse Input Voltage - VR ...................................................................... 3 V Supply Voltage - VCC ........................................... 7 V (1 Minute Maximum) Output Collector Current - IO ........................................................... 50 mA Output Collector Power Dissipation .............................................. 85 mW Output Collector Voltage - VO* ............................................................... 7 V Total Package Power Dissipation .................................................. 250 mW
*Selection for higher output voltage up to 20 V is available.
Recommended Operating Conditions Parameter Input Voltage, Low Level Input Current, High Level Supply Voltage, Output Fan Out @ RL= 1 k Operating Temperature Output Pull-up Resistor Symbol VFL IFH VCC N TA RL -40 330 Min. 0 2 4.5 Max. 0.8 10 5.5 5 85 4k Units V mA V TTL Loads C
4
Package Outline Drawing Standard DIP Package
9.40 (0.370) 9.90 (0.390) 8 7 A 6 7601 YYWW PIN ONE 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES). 5
TYPE NUMBER* DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310)
0.18 (0.007) 0.33 (0.013)
5 TYP.
3.56 0.13 (0.140 0.005) PIN ONE
4.70 (0.185) MAX.
PINOUT DIAGRAM N/C 1 8 7 6 5 VCC N/C VOUT GND
0.51 (0.020) MIN. 2.92 (0.115) MIN.
ANODE 2 CATHODE 3
0.76 (0.030) 1.24 (0.049)
0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) N/C 4
*TYPE NUMBER FOR: HCPL-7601 = 7601 HCPL-7611 = 7611
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
Gull Wing Surface Mount Option 300*
8
7
6
5
DIMENSIONS IDENTICAL TO STANDARD DIP EXCEPT AS NOTED.
1
2
3
4
9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) 0.255 0.075 (0.010 0.003)
0.51 0.130 (0.020 0.005)
0.635 0.25 (0.025 0.010) 12 NOM.
* REFER TO OPTION 300 DATA SHEET FOR MORE INFORMATION. NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
5
Solder Reflow Temperature Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
Recommended Pb-free IR Profile
TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC.
tp Tp TL 260 +0/-5 C 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C
TEMPERATURE
Tsmax Tsmin
RAMP-DOWN 6 C/SEC. MAX.
ts PREHEAT 60 to 180 SEC. 25 t 25 C to PEAK
tL
60 to 150 SEC.
TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C
Note: Non-halide flux should be used.
6
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Description Installation classification per DIN VDE 0109*/12.83, Table 1 for rated mains voltage 300 VRMS for rated mains voltage 600 VRMS Climatic Classification Pollution Degree (DIN VDE 0109/12.83)* Maximum Working Insulation Voltage VIORM VPR = 1.6 X VIORM 2 600 VRMS 848 Input to Output Test Voltage, Method b** Production test with tP = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** Production test with tP = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage, tTR = 10 sec) Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 16) Case Temperature Input Power Output Power Insulation Resistance at TSI, VIO = 500 V RIS VPR 960 1357 VPR = 1.2 X VIORM VPR 720 1018 VTR 6000 Vpeak VRMS Vpeak VRMS Vpeak Vpeak Symbol Characteristics I-IV I-III 40/85/21 Unit
TSI PSI,Input PSI,Output 1011
175 80 250
C mW mW
* This part may also be used in Pollution Degree 3 environments where the rated mains voltage is 300 VRMS (per DIN VDE 0190/12.83). ** Refer to the front of the optocoupler section of the current Optoelectronics Designers Catalog for a more detailed description of IEC/EN/DIN EN 60747-5-2 and other product safety regulations.
Insulation Related Specifications Parameter Minimum External Clearance (External Air Gap) Minimum External Creepage (External Tracking) Minimum Internal Clearance (Internal Plastic Gap) Comparative Tracking Index Isolation Group (per DIN VDE 0109) CTI Symbol L (IO1) L (IO2) Value 7.0 8.0 0.5 175 IIIa Units mm mm mm V Conditions Measured from input terminals to output terminals Measured from input terminals to output terminals Through insulation distance from conductor to conductor DIN IEC 112/VDE 303 P1 Material Group
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Electrical Specifications Over recommended temperature (TA = -40C to 85C) unless otherwise specified. (See note 1.) Parameter Input Threshold Current High Level Output Current Low Level Output Voltage High Level Supply Current Low Level Supply Current Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Input Diode Temperature Coefficient Input-Output Insulation Resistance (Input-Output) Capacitance (Input-Output)
*All typicals at TA = 25C, VCC = 5 V.
Symbol ITH IOH VOL ICCH ICCL VF BVR CIN VF/TA
Min.
Typ.* 1 3 0.35 4.75 6
Max. 2 100 0.6 7 10 1.85
Units mA A V mA mA V V
Test Conditions VCC = 5.5 V, IO 13 mA, VO = 0.6 V VCC = 5.5 V, VO = 5.5 V VFL = 0.8 V VCC = 5.5 V, IF = 2 mA, IOL (Sinking) = 13 mA VCC = 5.5 V, IF = 0 mA VCC = 5.5 V, IF = 4 mA IF = 4 mA IR = 100 A VF = 0, f = 1 MHz IF = 4 mA
Fig. 5 1 2, 4, 6
Note
1.2 3
1.5
3
72 -1.6
pF mV/C
3
VISO RI-O
3750 1012 1011 1013
VRMS
RH 50%, t = 1 min. TA = 25C TA = 25C TA = 100C VI-O = 500 V
3, 9 3
CI-O
0.6
pF
f = 1 MHz, VI-O = 0 Vdc
3
8
Switching Specifications Over recommended temperature (TA = -40C to 85C), VCC = 5 V, CL = 15 pF Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Skew Output Rise Time (10% - 90%) Output Fall Time (10% - 90%) Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level Symbol tPLH Device Min. 25 25 Typ.* 58 55 Max. Unit 75 100 75 100 100 120 75 100 55 40 75 40 58 24 10 ns Test Conditions TA = 25C TA = 25C IF = 2 mA, RL = 1 k IF = 4 mA RL = 350 IF = 2 mA RL = 1 k IF = 4 mA RL = 350 RL = 1 k RL = 350 RL = 1 k RL = 350 RL = 1 k RL = 350 RL = 350 - 1 k 13 Fig. Note 7, 8, 4, 10 10
35 tPHL 25
73 57
TA = 25C TA = 25C
7, 9, 5, 10 10
|tPHL-tPLH| tPSK trise
16 4
IF = 2 mA IF = 4 mA IF = 2 mA IF = 4 mA IF = 2 mA IF = 4 mA IF = 2 - 4 mA
11, 12
4, 5 6, 10
tfall
13
CMH
HCPL7601 HCPL7611
1,000
5,000
VCM = 50 V
10,000
15,000
VCM = 1000 V
IF = 0 mA Vo(min) = 2 V RL = 350 - 1 k TA = 25C
14
7
CML
HCPL7601 HCPL7611
1,000
5,000
V/s
2,000
5,000
10,000
15,000
IF = 2 - 4 mA RL = 350 - 1 k VCM = 50 V IF = 2 mA RL = 1 k VCM = 1000 V IF = 4 mA RL = 350 VCM = 1000 V
Vo(max) = 0.8 V TA = 25C
14
8
*All typicals at TA = 25C, VCC = 5 V.
9
Notes: 1. Bypassing of the power supply line is required with a 0.1 F ceramic disc capacitor adjacent to each optocoupler, as illustrated in Figure 15. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Device considered a two terminal device: pins 1 , 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 4. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse.
5. The tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. 6. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the operating condition range. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V). This specification
assumes that good board layout procedures were followed to reduce the effective input/output capacitance as shown in Figure 15. 9. In accordance with UL and CSA requirements, each optocoupler is proof tested by applying an insulation test voltage 5000 Vrms for one second (leakage detection current limit, II-O 5 A). 10. AC performance at IF = 4 mA is approximately equivalent to the HCPL2601/11 at IF = 7.5 mA for comparison purposes.
IOH - HIGH LEVEL OUTPUT CURRENT - A
VOL - LOW LEVEL OUTPUT VOLTAGE - V
VCC = 5.5 V VO = 5.5 V VIN = 0.8 V 10
VCC = 5.5 V IF = 2 - 4 mA 0.5
IF - INPUT FORWARD CURRENT - A
15
0.6
10-1 TA = 25 C 10-2 -3 10 -4 10 -5 10 -6 10 0.8 TA = 85 C TA = -40 C
0.4
IO = 16.0 mA
5
0.3
IO = 13.0 mA
0 -60 -40 -20
0
20
40
60
80 100
0.2 -60 -40 -20
0
20
40
60
80 100
1.0
1.2
1.4
1.6
1.8
2.0
TA - TEMPERATURE - C
TA - TEMPERATURE - C
VF - INPUT FORWARD VOLTAGE - V
Figure 1. High level output current vs. temperature.
Figure 2. Low level output voltage vs. temperature.
Figure 3. Typical input forward current vs. input forward voltage.
IOL - LOW LEVEL OUTPUT CURRENT - mA
ITH - INPUT THRESHOLD CURRENT - mA
5.0
VO - OUTPUT VOLTAGE - V
2.5
4.0
RL = 350 RL = 1 k RL = 4 k
2.0
VCC = 5.0 V VO = 0.6 V IO = 13.0 mA
55
50 IF = 4 mA 45 IF = 2 mA
3.0
1.5
2.0
1.0
40
1.0
0.5
35 VCC = 5 V VOL = 0.6 V 30 -50 -30 -10 0 10 30 50 70 90
0
0
0.5
1.0
1.5
2.0
0 -60 -40 -20
0
20
40
60
80 100
IF - FORWARD INPUT CURRENT - mA
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 4. Output voltage vs. forward input current.
Figure 5. Input threshold current vs. temperature.
Figure 6. Low level output current vs. temperature.
10
+5 V PULSE GEN. ZO = 50 tf = tr = 5 ns IF 1 2 INPUT MONITORING NODE RM 3 4 VCC 8 7 6 *CL GND 5 0.1F BYPASS RL OUTPUT VO MONITORING NODE
tPLH - PROPAGATION DELAY - ns
120 110 100 90 80 70 60 50 40 30 -50
VCC = 5 V TA = 25 C IF = 2-4 mA, RL = 4 k
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. IF INPUT IF tPHL OUTPUT VO tPLH 50% IF
IF = 2-4 mA, RL = 1 k
IF = 2-4 mA, RL = 350 -30 -10 0 10 30 50 70 90
1.5 V
TA - TEMPERATURE - C
Figure 7. Test circuit for tPHL and tPLH.
Figure 8. tPLH - Propagation delay vs. temperature.
PULSE WIDTH DISTORTION (tPHL- tPLH) - ns
100
tPHL - PROPAGATION DELAY - ns
tP - PROPAGATION DELAY - ns
90 80
VCC = 5 V RL = 350 - 4 k TA = 25 C IF = 2 mA
120 110 100 90 80 70 60 50 40 30 1 TPLH @ RL = 350 2 3 4 5 6 7 TPLH @ RL = 4 k
VCC = 5 V TA = 25 C
30 15 0
IF = 2 mA, RL = 350 IF = 2 mA, RL = 1 k IF = 4 mA, RL = 350 IF = 4 mA, RL = 1 k
70 60 50 40 30 -50 -30 -10 0 10 30 50 70 90 IF = 4 mA
TPHL @ RL = 350 - 4 k TPLH @ RL = 1 k
-15 -30 -45 -60 -50 IF = 4 mA, RL = 4 k -30 -10 0 10 30 IF = 2 mA, RL = 4 k
8
9 10 11
50
70
90
TA - TEMPERATURE - C
IF - INPUT CURRENT - mA
TA - TEMPERATURE - C
Figure 9. tPHL - Propagation delay vs. temperature.
PULSE WIDTH DISTORTION (tPHL - tPLH) - ns
Figure 10. Propagation delay vs. input current.
Figure 11. Pulse width distortion vs. temperature.
30 20 10 0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 10 12 RL = 1 k RL = 4 k RL = 350 VCC = 5 V TA = 25 C
tRISE, tFALL - RISE, FALL TIME - ns
330 320 310 300 290 60 40 RL = 350 20 RL = 1 k RL = 4 k VCC = 5.0 V IF = 2 - 4 mA
tFALL tRISE
RL = 350 , 1 k, 4 k 0 20 40 60 80 100
0 -60 -40 -20
IF - INPUT CURRENT - mA
TA - TEMPERATURE - C
Figure 12. Pulse width distortion vs. input current.
Figure 13. Rise and fall time vs. temperature.
11
IF B A VFF
1 2 3 4
VCC 8 7 6 5 0.1 F BYPASS RL
+5 V
OUTPUT VO MONITORING NODE
GND
VCM _ + PULSE GENERATOR ZO = 50 VCM (PEAK) 0V VO VO 0.35 V 5V SWITCH AT A: IF = 0 mA VO (MIN.) SWITCH AT B: IF = 2 or 4 mA VO (MAX.) CML CMH
VCM
Figure 14. Test circuit for common mode transient immunity and typical waveforms.
250 220 200
PSI, OUTPUT - mW
VCC BUS
PSI, INPUT - mW
150
0.1F
50 40 30 20 10 0
100
OUTPUT GND BUS 10 mm MAX. (SEE NOTE 1)
50
0
25
50
75
0 100 125 140 150 175
TA - TEMPERATURE - C
Figure 15. Recommended printed circuit board layout.
Figure 16. Dependence of safety-limiting data on ambient temperature.
12
(INPUT DRIVE CIRCUIT) VCC = 5 V I k (MAX.) 2 2N3906** *74LS04 3 SHIELD
DEVICE 8 390 6 0.1 F BYPASS 5 GND 2 VCC2
*ANY TTL GATE
**ANY PNP TRANSITOR CMOS OR TTL INTERFACE CIRCUIT 1N4148
VCC = 5 V
VCC = 5 V
620 (MAX.)
2
*74HC04
I k (MAX.)
*74LS05 3
*ANY CMOS HC OR HCT GATE CMOS DRIVE CIRCUIT FOR LOW POWER APPLICATIONS
*ANY OPEN COLLECTOR TTL OR OPEN DRAIN CMOS GATE INPUT DRIVE CIRCUIT FOR HIGH CMR APPLICATIONS
Figure 17. Recommended interface circuits.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2128EN AV01-0560EN July 6, 2007

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